Wafer Dicing
Our wafer dicing services provide precision die singulation for semiconductor, MEMS, and photonic devices. We deliver clean cuts with minimal chipping and excellent edge quality, ensuring high yield and device integrity across a wide range of substrate materials. Our processes are optimized for research, prototyping, and low-volume production, supporting both standard and complex device geometries with reliable and repeatable results.
Key capabilities
01
Precision wafer cutting
Cutting parameters can be selected to support different substrate materials, thickness ranges, and device layouts.
- Precision wafer cutting
- Street-aligned singulation
- Controlled cut path setup
- Research and prototype lot sizes
02
Support for fragile substrates
Substrates that are thin, brittle, or already processed may require more careful handling during singulation.
- Thin wafer awareness
- Glass, quartz, sapphire, and brittle material handling
- Reduced mechanical stress workflow
- Device-edge damage minimization
03
Custom die output formats
Die can be singulated according to custom chip size, layout spacing, and downstream packaging or testing needs.
- Custom die sizing
- Single chip or batch singulation
- Preparation for packaging and assembly
- Support for test-ready die handling
Workflow
How wafer dicing projects are typically prepared
Review substrate and device layout
The starting point is substrate material, wafer thickness, device spacing, and whether the wafer already includes sensitive films, structures, or topography near the dicing streets.
Define street width and die size
Cutting paths are selected according to the die layout, target chip dimensions, and the need to preserve edge quality without excessive material loss.
Select handling route for fragile or processed wafers
Thin wafers, brittle substrates, or wafers with completed structures may require special support, mounting, or lower-stress handling to reduce crack and chipping risk.
Prepare output for assembly or testing
Singulated die can then be routed into packaging, integration, wire bonding, or direct test workflows depending on the project stage.
Technical considerations
Key parameters for wafer dicing
| Parameter | Typical consideration | Engineering note |
|---|---|---|
| Substrate type | Si, glass, quartz, sapphire, ceramics, and other research materials | Material brittleness strongly affects the dicing route |
| Wafer thickness | Standard to thinned wafers | Thinner substrates generally require more careful handling |
| Street width | Defined by device layout and cut tolerance | Narrow streets increase alignment sensitivity |
| Die size | Standard or custom chip dimensions | Important for packaging and test fixture compatibility |
| Edge quality | Chipping, cracking, and die-edge integrity | Critical for fragile or high-value devices |
| Wafer condition | Blank, patterned, coated, or completed device wafer | Surface structures may change the handling approach |
| Post-dicing route | Loose die, tray handling, packaging, or test-ready output | Should be planned before singulation begins |
Typical materials and outputs
Typical applications
Prototype die singulation
Small-lot singulation for custom device validation and research-stage prototyping.
MEMS and sensor chips
Preparation of individual die for packaging, testing, and assembly of fragile microdevices.
Photonics and optics
Singulation of specialized chips and brittle substrate platforms for lab-scale integration.
Custom packaging prep
Output die prepared for wire bonding, chip mounting, and downstream assembly workflows.
Engineering considerations
Wafer dicing is often treated as a simple final step, but in practice it strongly affects downstream yield. Substrate fragility, edge chipping, thin-wafer handling, and output die format all influence whether singulated chips are ready for packaging and test without damage or loss.
Need wafer singulation for a prototype or custom lot?
Tell us your substrate, die size, and output format. We can help define a practical dicing route for research and device development.