UV Photolithography
High-resolution UV patterning for micro- and nano-scale device fabrication. We support a wide range of photoresist systems, substrates, and multi-layer process flows for research and prototype applications.
Standard process flow
How UV photolithography works at DR Research Foundry
Substrate preparation & cleaning
The substrate is cleaned using solvent and/or oxygen plasma to remove organic contamination and ensure strong resist adhesion. An HMDS adhesion promoter layer may be applied depending on substrate type and resist system.
Photoresist coating
Photoresist is spin-coated onto the substrate at controlled speed and acceleration to achieve the target film thickness (0.5 µm to >100 µm). Thickness is tuned by resist viscosity and spin parameters. A soft bake removes residual solvent and stabilizes the film.
Mask alignment & UV exposure
The photomask is aligned to existing features on the substrate (for multi-layer processes) using our mask aligner with ±0.5–1 µm overlay accuracy. The substrate is then exposed to i-line (365 nm) UV radiation for a calibrated dose, selectively crosslinking or scissioning the resist in the exposed regions.
Post-exposure bake (PEB)
For chemically amplified resists and certain deep-UV systems, a post-exposure bake drives the acid-catalyzed deprotection reaction. PEB conditions (temperature and time) are critical to resolution and CD control, and are optimized for each resist system.
Development
The exposed substrate is immersed in or puddle-developed with an aqueous alkaline developer (e.g. TMAH) for positive resists, or a solvent-based developer for negative resists. Development time and agitation are tightly controlled to achieve target critical dimensions with sharp sidewall profiles.
Inspection & hard bake (optional)
Pattern quality is inspected optically for CD uniformity, defects, and alignment. For processes requiring etch or ion implantation mask, a hard bake hardens the resist to improve etch resistance and thermal stability.
Downstream processing & resist strip
The patterned substrate proceeds to etching, deposition, doping, or lift-off as required. After the downstream process, photoresist is stripped using solvent or oxygen plasma, leaving the completed pattern on the substrate surface.
Technical specifications
System capabilities & process parameters
| Parameter | Specification | Notes |
|---|---|---|
| Exposure wavelength | i-line, 365 nm | Broadband UV also available |
| Resolution (min. feature) | 1–2 µm | Resist & process dependent |
| Overlay accuracy | ±0.5–1 µm | Multi-layer alignment |
| Resist thickness range | ~0.5 µm – >100 µm | Spin speed & viscosity controlled |
| Resist polarity | Positive & negative systems | AZ, S1800, SU-8, ma-N, etc. |
| Wafer size | Up to 6 inches (150 mm) | Chips & diced pieces accepted |
| Exposure mode | Contact, proximity, projection | Contact preferred for best resolution |
| Mask type | Chrome-on-quartz, emulsion, film | 5" & 7" standard mask sizes |
| Multi-layer support | Yes — full alignment stack | Registration marks required |
| Developer chemistry | TMAH (aqueous), solvent-based | Puddle & immersion development |
Supported photoresist systems
Positive photoresists
UV-exposed regions become soluble in developer. Ideal for standard lift-off, etch masking, and general device patterning. Best resolution for most applications.
Negative photoresists
Exposed regions crosslink and remain after development. Suited for thick structures, vertical sidewalls, MEMS, and microfluidic mold fabrication.
Specialty & bilayer systems
Bilayer and image reversal systems for controlled undercut profiles in lift-off, thick-film high-aspect-ratio structures, and temperature-stable device applications.
Typical applications
MEMS & sensors
Pressure sensors, accelerometers, gyroscopes, and RF MEMS requiring multi-layer patterning and thick resist structures.
Semiconductor devices
Transistor gates, ohmic contacts, isolation regions, and interconnect layers on Si, SiC, GaN, and other substrates.
Microfluidics
SU-8 master mold fabrication for PDMS soft lithography channels, mixers, and lab-on-chip device structures.
Metal lift-off
Bilayer resist patterning for controlled undercut profiles enabling clean metal lift-off for contacts and electrodes.
Photonics & optics
Waveguide cladding, grating definition, photonic crystal templates, and optical MEMS patterning on Si and SiO₂.
Research & process development
Rapid mask iteration, dose-focus matrix studies, and new resist qualification for emerging semiconductor platforms.
Substrate compatibility
Supported substrate materials
Silicon (Si)
Standard & SOI wafers
Silicon Carbide (SiC)
4H-SiC, 6H-SiC
GaN on Si / Sapphire
HEMT & LED structures
Sapphire
Optical & optoelectronic
Glass & Quartz
Fused silica, borosilicate
III-V Compounds
GaAs, InP, InGaAs
Polymers & Flex
Polyimide, PET, PDMS
Custom substrates
Upon feasibility review
Lithography method comparison
UV photolithography vs. other patterning techniques
| Method | Min. feature size | Throughput | Best for |
|---|---|---|---|
| UV Photolithography | 1–2 µm | High | Most device fabrication, multi-layer, prototyping |
| E-beam Lithography | <20 nm | Low | Sub-micron features, nanophotonics, research |
| Laser Direct Write | 1–5 µm | Medium | Maskless, rapid iteration, irregular shapes |
| Soft Lithography (PDMS) | ~1 µm | High (replica) | Microfluidics, lab-on-chip, bio devices |
| Nanoimprint | <10 nm | High | High-volume sub-100 nm patterning |
Ready to discuss your lithography project?
Share your design files, resist requirements, or process targets — our PhD engineers will assess feasibility and respond within 48 hours.