Multi-layer Alignment
Mask alignment and multilayer lithography services enable precise layer-to-layer registration for complex semiconductor and MEMS device fabrication. We achieve overlay accuracy down to ±0.5–1 µm, ensuring reliable alignment for advanced multi-layer structures in research, prototyping, and small-scale production.
Alignment process flow
How multi-layer alignment works at DR Research Foundry
Alignment mark design & first layer definition
Alignment marks are incorporated into the photomask or e-beam design at the first layer. Marks are placed in the die corner, scribe lane, or dedicated alignment field. Common geometries include cross, box-in-box, verniers, and L-shaped targets. The first layer establishes the reference coordinate system for all subsequent layers.
Substrate loading & pre-alignment
The substrate is loaded onto the mask aligner stage. Coarse pre-alignment is performed using wafer flat or notch registration and stage-level sensors. The substrate is vacuum-clamped to prevent movement during fine alignment. For warped or non-standard substrates, additional fixturing may be applied.
Optical alignment & mark detection
The mask aligner microscope locates the alignment marks on both the substrate (from the previous layer) and the photomask simultaneously. The operator or automated system adjusts X, Y, and θ (rotation) to bring the mask marks into coincidence with the substrate marks. Alignment is performed at two or more mark locations to correct for both translation and rotation errors.
Gap setting & exposure mode selection
The mask-substrate gap is set according to the exposure mode: contact (0 µm gap, best resolution), soft contact, proximity (10–50 µm gap), or projection. Contact mode achieves the highest resolution but risks mask contamination; proximity mode extends mask lifetime with a small resolution penalty. Gap is calibrated for each process.
UV exposure
With alignment confirmed and gap set, the substrate is exposed to calibrated UV dose (mJ/cm²). Exposure time is optimized per resist type and thickness. For critical layers, dose is verified against a calibration wafer before production exposure to ensure CD consistency across the run.
Overlay measurement & verification
After development, overlay error is measured at multiple die locations using vernier targets or box-in-box overlay marks under an optical microscope. Overlay values in X and Y are recorded. If overlay exceeds the process tolerance, the resist is stripped and the step is repeated — ensuring only compliant layers proceed to downstream processing.
Repeat for subsequent layers
Each additional layer follows the same alignment sequence, referencing the marks established at Layer 1. For deep-stack processes (5+ layers), cumulative alignment error is tracked and corrected. Alignment data is logged per wafer to support process traceability and yield analysis.
Technical specifications
System capabilities & alignment parameters
| Parameter | Specification | Notes |
|---|---|---|
| Overlay accuracy | ±0.5–1 µm | Substrate & process dependent |
| Alignment modes | Manual & semi-automatic | Two-point mark registration |
| Exposure modes | Contact, soft contact, proximity | Gap 0–50 µm selectable |
| Alignment mark types | Cross, box-in-box, vernier, L-mark | Custom mark design supported |
| Max. wafer size | Up to 6 inches (150 mm) | Chips & diced pieces accepted |
| Exposure wavelength | i-line 365 nm (UV) | Broadband available |
| Min. feature size | 1–2 µm (UV mode) | EBL available for sub-µm layers |
| Max. layer count | Process dependent — 10+ layers supported | Cumulative error tracked per layer |
| Overlay measurement | Optical — vernier & box-in-box | Measured post-development |
| Rework policy | Resist strip & redo if out-of-spec | Included in standard process |
Example multi-layer device stack
Typical 4-layer MEMS process build-up
Each layer is aligned to Layer 1 reference marks. Overlay is verified after each lithography step before proceeding.
Alignment mark geometries
Cross & plus marks
The most common alignment mark type. Simple to fabricate and detect optically. Used for both X/Y translation and rotational alignment correction.
Box-in-box overlay targets
Outer box patterned on Layer N-1, inner box on Layer N. Overlay error measured as centroid offset between boxes. Quantitative and suitable for SEM or optical measurement.
Vernier scales
Interlocking linear gratings with slightly different pitches. Misalignment read directly from which vernier division aligns — analogous to a mechanical vernier caliper. Resolutions down to 0.1 µm achievable.
Overlay error sources & controls
Common error sources
- Thermal expansion Wafer and chuck temperature changes cause dimensional drift between layers
- Substrate warpage Bowed wafers cause local Z-height variation and defocus at field edges
- Stage backlash Mechanical hysteresis in X/Y/θ stage introduces systematic offset
- Mark degradation Deep etching or thick films can obscure alignment marks on lower layers
- Magnification mismatch Process-induced substrate shrink/expand between layers
Our process controls
- Temperature stabilization Chuck and cleanroom temperature controlled to ±0.5°C
- Mark preservation Mark layers designed to survive downstream etch and deposition steps
- Two-point alignment Marks at two separated locations correct both translation and rotation
- Post-develop overlay check Every layer measured before proceeding — rework if out of spec
- Process traceability Overlay data logged per wafer per layer for yield tracking
Typical applications
MEMS devices
Pressure sensors, accelerometers, gyroscopes, and RF MEMS requiring precise structural layer registration and electrode alignment.
Semiconductor devices
Multi-layer transistor fabrication, ohmic contact opening, gate definition, and interconnect patterning on Si, SiC, and GaN.
Photonic integrated circuits
Waveguide-to-coupler alignment, grating coupler placement, and metal contact registration on Si or InP photonic platforms.
Microfluidic systems
Multi-layer channel and valve structures requiring precise layer-to-layer registration for functional device operation.
Sensor arrays
Chemical, biological, and physical sensor arrays with multi-layer electrode and sensing element registration on chip.
Research prototyping
Rapid multi-layer prototype iteration for academic and industrial R&D — with overlay data provided for process characterization.
Need multi-layer alignment for your device?
Share your layer stack, overlay requirements, and substrate — our team will design the alignment strategy and respond within 48 hours.