E-beam Lithography
Sub-20 nm patterning capability for nanoscale device research, photonic structures, and custom nanoelectronic applications. Maskless, flexible, and compatible with GDSII design files.
Standard process flow
How E-beam lithography works at DR Research Foundry
Substrate preparation & cleaning
The substrate is cleaned by solvent rinse and/or oxygen plasma to remove organic contamination. Surface treatment with HMDS may be applied to improve resist adhesion on oxide or nitride surfaces. Cleanliness is critical at EBL scale — even small particulates can cause defects at sub-100 nm feature sizes.
Resist coating
Electron-beam resist is spin-coated to the target thickness — typically 50–500 nm for high-resolution work, or thicker for lift-off applications. Common resists include PMMA (positive) and HSQ or ma-N (negative). Spin speed, resist concentration, and molecular weight are all tuned to the target CD and process.
Pattern design & GDSII file preparation
Your design is imported in GDSII or DXF format and fractured into the exposure field grid. Proximity effect correction (PEC) is applied to compensate for electron backscattering, which is essential for achieving uniform feature sizes across dense and isolated regions of the pattern.
E-beam exposure
A focused electron beam scans the substrate in a controlled raster or vector pattern, delivering a calibrated dose (µC/cm²) to each region. Beam current, accelerating voltage (typically 30–100 kV), and step size are optimized for the target feature size and resist system. High voltage reduces proximity effects and improves resolution for sub-50 nm features.
Development
For positive resists (e.g. PMMA), exposed areas are dissolved in MIBK:IPA developer. For negative resists (e.g. HSQ), unexposed areas are removed. Development time, temperature, and agitation are tightly controlled. Cold development (−15°C for PMMA) can further improve resolution and contrast for critical sub-20 nm applications.
Inspection & critical dimension measurement
Developed patterns are inspected by SEM for CD uniformity, edge roughness (LER/LWR), and defect density. CD measurements are compared to design targets and used to calibrate dose for subsequent exposures. This closed-loop process ensures consistent results across runs.
Downstream processing & resist removal
The patterned resist is used as an etch mask, lift-off template, or implantation mask for the subsequent process step. After processing, resist is removed by solvent strip (acetone/NMP for PMMA) or oxygen plasma. For HSQ, dilute HF may be required for full removal.
Technical specifications
System capabilities & process parameters
| Parameter | Specification | Notes |
|---|---|---|
| Min. feature size | Down to ~20 nm | Resist & process dependent |
| Accelerating voltage | 10–100 kV | Higher voltage → better resolution |
| Beam current range | pA – nA range | Resolution vs. throughput trade-off |
| Writing field size | Up to ~1 mm × 1 mm per field | Stitched for larger areas |
| Stitching accuracy | <50 nm field-to-field | Laser interferometry stage |
| Overlay accuracy | <30–50 nm | Multi-layer registration |
| Substrate size | Up to 6 inches (150 mm) | Chips & diced pieces accepted |
| Resist thickness | 50 nm – several µm | Optimized per application |
| File formats | GDSII, DXF, CIF | Proximity effect correction included |
| Proximity effect correction | Yes — Monte Carlo simulation | Critical for dense patterns |
Supported e-beam resist systems
Positive e-beam resists
Exposed regions are cleaved and become soluble in developer. Excellent resolution for sub-100 nm features; widely used for lift-off and etch mask applications.
Negative e-beam resists
Exposed regions crosslink and remain after development. Used for direct-write etch masks, hard mask patterning, and applications requiring high etch selectivity.
Bilayer & specialty systems
Bilayer stacks (e.g. MMA/PMMA) create controlled undercut profiles for clean metal lift-off at nanoscale. Conductive coatings prevent charging on insulating substrates.
Typical applications
Nanophotonics & plasmonics
Photonic crystal cavities, plasmonic nanostructures, metallic nanogap antennas, and near-field optical devices.
Nanoelectronics
Single-electron transistors, quantum dot arrays, nanowire contacts, and sub-50 nm gate definition on semiconductor substrates.
Photomask & template fabrication
Writing master masks for UV lithography, nanoimprint templates, and zone plate optics with sub-100 nm feature fidelity.
MEMS & nano-MEMS
Nanoscale resonators, cantilevers, nano-gap electrodes, and precision alignment marks for MEMS device integration.
2D materials & quantum devices
Contacts and gates on graphene, MoS₂, hBN heterostructures, and quantum dot / qubit device patterning.
Research & process development
Dose-contrast matrix experiments, new resist qualification, and rapid iteration without photomask fabrication lead time.
Substrate compatibility
Supported substrate materials
Silicon (Si)
Standard, SOI, Si/SiO₂
SiC
4H, 6H — with charge coat
GaN on Si / Sapphire
HEMT gate definition
Quartz / Fused silica
With conductive coating
III-V Compounds
GaAs, InP, InGaAs
2D material substrates
Graphene, MoS₂, hBN
Sapphire
Optical & optoelectronic
Custom substrates
Upon feasibility review
EBL vs. UV photolithography
When to choose E-beam over UV lithography
| Factor | E-beam Lithography | UV Photolithography |
|---|---|---|
| Resolution | Down to ~20 nm | 1–2 µm |
| Throughput | Low — serial writing | High — full wafer at once |
| Photomask required | No — maskless | Yes |
| Design flexibility | High — edit GDSII directly | New mask needed per revision |
| Cost per run | Higher | Lower at volume |
| Best use case | Sub-µm research, nanofabrication, first-pass prototypes | Multi-layer devices, larger features, higher volume |
Ready to discuss your EBL project?
Share your design, target feature size, and substrate — our PhD engineers will assess feasibility and respond within 48 hours.